In vertically oriented transistors, well-controlled material layer thickness define functional lengths, such as gate length (Lg), and material composition may be advantageously tailored to achieve band gap and mobility differentiation. Current drive can also be continuously scaled by lithographic patterning of the channel width (Wg) and corresponding cross-section of the nanowire. However, in practical applications, one may need to print nanowire features (e.g., holes) on the order of 15 nm or less in diameter while having very good critical dimension (CD) uniformity, good circularity, and of minimal feature pitch for highest density. In addition the channel pattern must be accurately aligned to the gate stack and contact metallization.
Lithographic printing of holes less than 15 nm with sufficient CD uniformity, circularity, and pitch is beyond the capability of known ArF or EUV resist. Techniques whereby holes are printed larger and then shrunk fail to achieve desired pitches (e.g., <30 nm). Such pitches are also below the resolution of even two mask patterning techniques, and as such would require at least three mask patterning steps along with a very aggressive shrink process employing an expensive lithography toolset.
Techniques to pattern a vertical nanowire transistor to dimensions below 15 nm and pitches below 30 nm, which are manufacturable at lower cost are therefor advantageous.